1. Field of The Invention
The present invention relates to video memory controllers for split-panel LCD displays. More particularly, the invention relates to video memory controllers for split-panel LCD displays in which a frame buffer and frame rate modulation are used to increase the refresh rate of the display.
2. State of the Art
Presently, desktop computers are typically equipped with a VGA color monitor, a cathode ray tube (CRT) having a resolution of 640.times.480 pixels. Most common are analog RGB monitors capable of displaying practically an unlimited variety of colors. Present day notebook computers, on the other hand, typically have a VGA monochrome liquid crystal display (LCD) or other flat-panel display. Although some notebook computers having color LCD displays are presently being offered, these displays are considerably more expensive than monochrome LCD displays. To increase the versatility of notebook machines, a CRT option is offered whereby the notebook computer may be used to drive an analog RGB display.
A CRT receives as its input a single stream of raster image data and displays this raster image data in a series of lines, which constitute a frame. Single-panel LCD displays operate in a similar manner. For a 640.times.480 panel, each line is actively displayed for only about 1/480 of the frame period (18 ms for a 60 Hz screen refresh rate). Video data is loaded into a line buffer four consecutive pixels at a time, and at the end of each scan line, the entire data for that line is transferred to a latch register that presents it to the line drivers. The data drives the panel drivers until the next line is loaded into the latch register, and so on.
Split-panel LCDs, on the other hand, are made of two segments, an upper segment and a lower segment, that operate in parallel and that require two parallel streams of data, one for each segment. Referring to FIG. 1A, the split-panel LCD 120 has two separate sets of drivers, one (125) for the upper half of the panel 121 and one (127) for the lower half of the panel 123, that together drive two scan lines simultaneously.
One approach to driving a split-panel LCD display uses a line buffer. Data is fetched from video memory alternately for different LCD display halves. As one scan line is fetched, the other is stored in a scan line buffer, and then both scan lines, one belonging to the upper half of the display and one belonging to the lower half of the display, are shifted out to the flat-panel and displayed. Both display lines are fetched from video memory at VGA graphics mode resolution (4 bits or 8 bits per pixel). If the video memory data path is operated at the same speed as for a CRT display of the same resolution, the resulting frame refresh rate results in poor picture quality. To maintain an acceptable screen refresh rate, the video memory data path in accordance with the line buffer approach has to operate at twice the speed relative to the CRT, resulting in increased power consumption.
In comparison with CRT displays, split-panel LCD displays have therefore not only suffered from (typically) a lack of color but, in many cases, poor display quality.
The lack of display colors may be addressed using a technique known as frame rate modulation. In frame rate modulation, a pixel's illumination state is controlled over the course of successive frames, enabling the visual impression of shades of grey to be produced in addition to the usual black and white of a monochrome display. Frame rate modulation is described, for example, in U.S. Pat. No. 5,185,602.
Using a half-frame buffer, frame rate modulation further enables a higher screen refresh rate to be achieved, addressing the second common drawback of split-panel LCD displays. In effect, frame rate modulation maps color or grey scale video data to be displayed at a pixel onto a temporal sequence of binary display data to be successively displayed at the pixel so as to create a visual impression of a shade of grey at that pixel. At the time the mapping is performed, not only are binary display data to be displayed during a current frame known, but binary data to be displayed during a next frame may also be determined.
Using a half-frame buffer, the video data may be read out of the video memory in the same manner as for CRT display. Referring to FIG. 1B, the left hand side of the figure represents a display sequence beginning at half-frame H. Video data is read out of video memory, first for the upper half-frame and then for the lower half-frame, and converted to binary display data, or shaded data, which is then displayed directly on the LCD display screen. This data, being displayed directly on the LCD display, is referred to as "direct current frame shaded data" (dcfsd). The right hand side of FIG. 1B represents a display sequence beginning one-half frame earlier than the display sequence on the left hand side of the figure, at half-frame (H-1). Otherwise, the two display sequences represent the same events. For each half-frame, as video data is read out of video memory and converted to shaded data, shaded data is produced not only for a current frame but for a next frame also. On both sides of FIG. 1B, the half-frames therefore occur in pairs U,U;L,L;U,U; etc., one-half frame of each pair being current frame shaded data, and another half-frame of each pair being next frame shaded data. The shaded data for the next frame is stored in the half-frame buffer, represented within the dashed lines in the center of FIG. 1B, and is read out of the half-frame buffer and displayed at the time of the next frame. This data is therefore displayed indirectly, via the half-frame buffer, and is referred to as "indirect next frame shaded data" (infsd).
Each half-frame, the contents of the half-frame buffer (upper half-frame or lower half-frame) are read out and displayed on the LCD display (upper half or lower half) before being overwritten by newly produced next frame shaded data. The sequence of operations therefore proceeds as follows:
Read out video data for the upper half-frame; PA1 Convert to shaded data; PA1 Display current shaded data on upper half of LCD panel; PA1 Read out and display on lower half of LCD panel shaded data previously stored in half-frame buffer for lower half-frame; PA1 Overwrite half-frame buffer contents with next shaded data for upper half-frame; PA1 Read out video data for the lower half-frame; PA1 Convert to shaded data; PA1 Display current shaded data on lower half of LCD panel; PA1 Read out and display on upper half-frame of LCD panel shaded data previously stored in half-frame buffer for upper half-frame; and PA1 Overwrite half-frame buffer contents with next shaded data for lower half-frame; etc.
Twice as many frames are displayed on the LCD panel as would be displayed on a CRT during the same time. The full LCD displays are therefore given the reference numerals 1.1, 1.2, 2.1, 2.2, etc., the integer portion of the reference numeral corresponding to CRT frame times and the decimal portion corresponding to a first or second LCD frame time within each CRT frame time. Because the frame rate is doubled as compared to a conventional CRT, the apparatus performing the described operations is referred to as a "frame accelerator".
Prior art flat-panel graphics controllers (such as the CL-GD6410 flat-panel graphics controller of the assignee) used an independent memory device, usually a 64K.times.4 or a 256K.times.4 dynamic random access memory (DRAM) as a half-frame buffer and frame accelerator for split-panel, dual-scan LCD displays. FIG. 2 illustrates a system solution using separate DRAMs for video memory and the half-frame buffer frame accelerator. Since at the time only 256K bit and 1M bit DRAMs were available, and since VGA displays require 2M bit of video memory, several DRAM devices were required just to implement the video memory. An additional DRAM having its control signals tightly coupled to the video data clock was used to implement the half-frame buffer. As a result, the DRAMs used for video memory were totally decoupled from the DRAM used for the half-frame buffer and for frame acceleration. In other words, the two memory arrays had separate address, data and control signals and operated out of synch with each other. Specifically, the frame accelerator operated off the video data clock (25 MHz or lower frequency), while the video memory controller operated off an independent higher frequency clock (Memory Clock, or MCLK) having a frequency of 36 MHz to 50 MHz, depending on the DRAM speed used. This arrangement simplified the system design, inasmuch as the data to and from the frame accelerator was exchanged at the speed of the video data clock.
The block diagram of FIG. 3 shows in greater detail the dual scan LCD flat-panel VGA graphics controller system of FIG. 2, with its separate DRAMs for video memory and for the half-frame buffer frame accelerator. Two independent DRAM controllers, the video memory controller VMC and the frame accelerator DRAM controller 21, operate off two different clocks (the memory clock and the video dock clock, respectively). The frame accelerator DRAM controller 21 executes read-modify-write cycles to the 64K.times.4 or 256K.times.4 DRAM, reading the indirect data for one flat-panel half and immediately writing the new data for the current flat-panel half, but with the frame modulation for the next frame.
The blocks 23, 25, 27, 29, 31, 33, 35, and 37 in FIG. 3 are common to virtually all VGA controllers and operate in a manner well-known in the art to provide an analog RGB signal to a CRT. The LCD block 40 and the frame accelerator 50, realized by the frame accelerator DRAM controller 21 and the half-frame buffer 47, provide frame rate modulated upper data and lower data at an accelerated frame rate to a monochrome dual scan flat-panel 51. Within the LCD Block 40, a Sum-to-Grey block 41 receives an 18 bit digital RGB signal produced by the VGA ram 33 (6 bits for each color R, G and B) and performs a summing operation to produce 6 bits of grey scale data. From the 6 bit grey scale data, the frame rate modulation block 43 produces shaded data, 1 bit of current frame shaded data (csfd) and 1 bit of next frame shaded data (nfsd). Four bits of current frame shaded data and 4 bits of next frame shaded data are accumulated in a dual 1-to-4 serial-to-parallel converter 35. The 4 bits of current frame shaded data (dcsfd) are displayed directly on the monochrome dual scan flat-panel 51, and the next frame shaded data is input to the frame accelerator 50. At the same time, indirect current frame shaded data (icsfd) previously stored in the half-frame buffer is output by the frame accelerator and displayed on the monochrome dual scan flat-panel 51. The direct current frame shaded data and the indirect current frame shaded data may be displayed on either the upper panel or the lower panel of the monochrome dual scan flat-panel 51 in accordance with a control signal produced by the LCD Block 40.
With the advent of 16M bit DRAMs, there is now available in one memory device sufficient memory space to physically accommodate both the VGA video memory and the required 19.2 KByte half-frame buffer with considerable memory space to spare. Integration of both the video memory and the dual scan LCD display half-frame buffer frame accelerator in one memory device would reduce considerably the form factor of a dual scan LCD display controller system without affecting frame refresh rate or picture quality. Power savings would also be achieved relative to the use of two memory arrays and relative to the line buffer approach of driving dual scan panels, which requires higher video clock rates to achieve similar results in screen refresh rates. Because dual scan LCD displays are used mostly with portable systems working on a battery, saving power in the LCD display system is very important in order to extend the time a system can operate without a battery recharge.
Significant technical obstacles, however, have prevented the video memory and the half-frame buffer frame accelerator from being previously integrated in one memory device. Frame accelerator integration in one DRAM leads to a performance bottleneck related to DRAM bus bandwidth. Normal video memory read cycles, CPU read and write memory cycles to video memory, memory refresh cycles, and flat-panel read and write cycles to and from the frame accelerator all compete for DRAM bandwidth.